The present invention relates to the field of electrochemical deposition, and more particularly to a method of electroless plating a metal cap over a conductive interconnect and to chalcogenide-based memory devices that include such structure.
The performance characteristics and reliability of integrated circuits have become increasingly dependent on the structure and attributes of the vias and interconnects which are used to carry electronic signals between semiconductor devices on integrated circuits or chips. Advances in the fabrication of integrated circuits have resulted in increases in the density, number of semiconductor devices contained on a typical chip, and speed. Interconnect structure and formation technology has not advanced as rapidly, and is increasingly becoming a limitation on the signal speed of integrated circuits.
Present-day, high-performance integrated circuits typically have multiple layers of metal conducting lines. These metal layers are separated by relatively thick, insulating layers of materials such as silicon dioxide. Vias are made through the insulating layers to make connections between the metal lines. It is often desirable that the metal conducting lines be maintained in as much of a plane as possible to avoid undue stresses on the metal lines. A tungsten metal plug is often used to fill the via in the insulating layer covering a first metal pad or line so that the overlying film remains on the planar surface of the insulating layer. Without the plug, the overlying film must dip into the via to make contact with the underlying first metal.
A layer of titanium (Ti) is typically placed in contact with the underlying first metal as an adhesion layer for the subsequent tungsten contacts. The via is then filled by depositing tungsten metal, typically by a chemical vapor deposition (CVD) process. When high aspect ratio vias are to be filled, tungsten deposited on the sidewalls of the via during the deposition process may pinch off the opening, leaving a void termed a “keyhole” buried within the via. When excess tungsten from the CVD deposition process is removed, typically using a chemical-mechanical planarizing (CMP) process, the buried “keyholes” may be opened up, leaving exposed voids at the tops of the vias. Such voids adversely affect the subsequent formation of other layers and the electrical connections between layers.
Accordingly, the need still exists in the art for a process of providing metal-filled high aspect ratio vias that result in good electrical connections to subsequent layers of a fabrication process for semiconductor devices.